| EE Times-India | eetindia | | | | Device Cost Range |
| FPGA is an electronic device that helps the design | | | | Minimum Cents/MMAC for FPGA |
| engineers to create custom logic for high | | | | Minimum Cents/MMAC for DSP |
| commutation signal processing and DSP is a CPU for | | | | High (>1000 MMAC) |
| signal processing applications that has been designed | | | | $100 to $300 |
| to execute signal processing algorithms for which the | | | | 2.9 |
| principle algorithm that is multiply-and-accumulate | | | | 5.8 |
| operation is similar to all other algorithms. In the | | | | $300 to $1000 |
| implementation of DSP (Digital Signal Processor) and | | | | 4.2 |
| FPGA (Field Programmable Gate Array), design | | | | 13.4 |
| engineers focus on various parameters such as: | | | | $1000 to $10000 |
| Power Consumption, System Performance, Form | | | | 20 |
| Factor, System’s Future Upgrade Ability, | | | | Medium (300 to 1000 MMAC) |
| Non-Recurring Engineering (NRE) Investment, | | | | $10 to $30 |
| Bill-of-Materials (BOM) Cost and Project Risk. Generally | | | | 1.4 |
| the engineers know about DSP but not completely | | | | 1.6 |
| aware of FPGA and hence this creates a situation | | | | $30 to $100 |
| where they need to select any one of them. | | | | 2.8 |
| | | | | 3 |
| These devices are very different from each other | | | | Low ( |
| and designed to serve different purposes. DSP | | | | < $10 |
| provide an optimized platform for signal processing | | | | 1.8 |
| algorithms implemented in software whereas FPGA | | | | |
| were for glue logic. Nowadays, there are certain | | | | |
| applications where both these devices deliver | | | | For applications with performance requirements |
| optimum solutions. FPGA is the better choice for | | | | above 1000 MMAC, FPGA/DSP Hybrid solutions are |
| networking applications and DSP is at its best in video | | | | often the ideal solution. These applications often |
| applications. This example indicates their performance | | | | include multiple signal processing algorithms, some |
| has gone through a remarkable change over the | | | | of which have low performance requirements. In |
| years. | | | | such cases, relatively inexpensive DSPs can |
| | | | | implement the algorithms with low-to-medium |
| In terms of cost-performance values, DSP and FPGA | | | | performance requirements, leaving the |
| are compared in three MMAC (Millions of | | | | higher-performance algorithms to FPGAs. For designs |
| Multiply-Accumulate Operations per Second) | | | | with MMAC requirement below 300 MMAC, DSPs |
| performance categories viz. High, Medium and Low. | | | | are in general the optimum solution from cost |
| MMAC is the number of fixed-point-32-bit or | | | | performance perspective. For designs with MMAC |
| single-precision floating-point multiply-and-accumulate | | | | requirement between 300 and 1000 MMAC, the DSP |
| operations that can be executed in units of millions | | | | is generally preferable when it comes with application |
| per second. The table given below can help the | | | | specific resources (such as video/audio ports, ARM |
| design engineers in making the right selection | | | | processor, etc., as is the case with the DaVinci |
| between DSP and FPGA. | | | | digital media processors). When a DSP with |
| | | | | application specific resources does not exist, other |
| | | | | aspects of the design must be considered. |
| MMAC Category | | | | |